Introduction

A Field-Programmable Gate Array (FPGA) is an integrated circuit, inside which you can wire up a logic circuit using software code. With this you can achieve results you cannot do with a microprocessor, such as true parallelism without timesharing. You can wire up large circuits. Recently, an open source toolchain has become available to translate the Verilog Hardware Description Language (HDL) into programs for two FPGA parts from Lattice Semiconductor. Both parts are available on evaluation boards, the larger part's board costs $50. This FPGA contains nearly 8,000 lookup table cells, and two Phase-Locked Loops (PLLs) for generating clocks. That is a lot of capability for the price.

Building Icestorm on Ubuntu 14 for synthesis, place and route, programming

See "Where are the Tools? How to install?" in here.

Installing Icarus Verilog on Ubuntu 14 for simulation

Start here and continue here.

Installing USB cable on Ubuntu 14 for programming with iceprog

Add the file /etc/udev/rules.d/53-lattice-ftdi.rules containing:

ACTION=="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE:="666"

Project: blinky lights of counter bits

Originally from here, now here.

Project: PWM light which smoothly changes brightness

Originally from here, demo board version here.

Project: adder button test

This tests adder buttons. Each of the five buttons is Normally Open (NO), and grounds its FPGA input pin when pressed. See pinout.svg for which FPGA pins are used.

Project: adder, with buttons, and with seven segment displays

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hg clone --insecure http://www.workver.com/full-adder-bb
hg clone --insecure http://www.workver.com/7segment
hg clone --insecure http://www.workver.com/full-adder-bb-7seg
cd full-adder-bb	# or
cd 7segment		# or
cd full-adder-bb-7seg
make help

This project has both synthesize and simulate makefile targets. Simulations test the whole project, button debouncing, and seven segment displays separately. Try make help for details. These projects need an additional circuit boards containing buttons and seven segment displays to operate them. See the adder button test above for button board details. Note: The top button does not work properly in full-adder-bb's Verilog processed through Icestorm, for unknown reasons. It blinks the button pressed light, but does not set the associated bit. Similarly, in full-adder-bb-7seg the top button doesn't work and the right button sets the bit on the LEDs and in the sum but not in the seven segments digit.

Project: Forth environment on soft CPU

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git clone https://github.com/jamesbowman/swapforth
cd swapforth/j1a/icestorm
iceprog icestorm/j1a8k.bin
python shell.py -h /dev/ttyUSB1

See also: http://www.excamera.com/sphinx/article-j1a-swapforth.html

Set leds to binary value

1 2 + .
-1 leds
0 leds

Blink leds in loop

: blink
  32 0 do
  i leds
  100 ms
  loop
;
blink

Compute date of Easter

new
#include ../demos/easter.fs
2017 .easter

Project: seven segment display

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hg clone --insecure http://www.workver.com/7segment
cd 7segment
make help

This project has both synthesize and simulate makefile targets. Simulations test the whole project, the seven segment number to segment encoding, and the seven segment digit multiplexing separately. Try make help for details.

This project needs an additional circuit board containing seven segment displays.

Web pages

yosys
yosys reddit  yosys stackoverflow
Learning Verilog with YoSys
J-Core Open Processor  Building a CPU from Scratch: jcore Design Walkthrough by Rob Landley & Jeff Dionne
Aboriginal Linux
What every programmer should know about memory, Part 1  Part 2  Part 3  Part 4  Part 5  Part 6  Part 7  Part 8  Part 9
Learning FPGA And Verilog A Beginner's Guide Part 1 -- Introduction  Part 2  Part 3  Part 4  Part 5  Part 6

Data sheets

iCE40HX-8K Breakout Board User Guide

iCE40(TM) LP/HX Family Data Sheet

iCE40 sysCLOCK PLL Design and Usage Guide, originally found here.

Memory Usage Guide for iCE40 Devices, originally found here.

iCE40 Programming and Configuration, originally found here.

Ubuntu 14 changes for programming with Diamond standalone programmer

For using Lattice Diamond standalone programmer on Linux, if you want to use it after using Lattice iCEcube2 synthesis, place and route.

The FlexLM license manager only looks at eth0 for an ethernet address to match with the license key from Lattice. If your laptop only has wireless, rename the wireless interface "wlan0" to "eth0" in /etc/udev/rules.d/70-persistent-net.rules.

Disable the ftdi_sio kernel module which makes the USB programmer cable not work for Diamond programmer on Linux. Add this line to /etc/udev/rules.d/53-lattice-ftdi.rules. I have not seen this udev code work, I remove the kernel module manually with lsmod | grep ftdi and rmmod ftdi_sio. The module reinstalls after a time delay, and can be removed after the Diamond programmer program is run, but before you start to program.

ATTRS{idVendor}=="0403", ATTRS{idProduct}=="6010", ATTRS{product}=="Lattice FTUSB Interface Cable", RUN+="/bin/sh -c 'echo $kernel > /sys/bus/usb/drivers/ftdi_sio/unbind'"
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sudo udevadm control --reload-rules

FPGA hardware

Lattice iCE40-HX8K

Numato Mimas v2 with Spartan 6

Complete soft computers

j-core is under active development. It runs Linux today to a serial console on a $50 Numato Mimas v2 FPGA board. They're building an FPGA board called the Turtle.

TEMLIB Implements Sun SPARCstation 5 on Xilinx Spartan 6, runs Linux RedHat 4.2, Linux Debian 4.0, Linux Aurora 1.0, NetBSD 5.1, OpenBSD 5.3, SunOS 4.1.4 / SunView, SunOS 4.1.4 / OpenLook, and NextStep 3.3.


Copyright © 1994, 1995, 1996, 1997, 1998, 1999, 2002, 2003, 2013, 2014, 2015, 2016, 2017, 2018 Brian Bartholomew
Version control: 95415322e7484412c20f1865760617268e7831b6 on 2018-06-18 16:00 -0400